请问如下程序是Verilog 还是VHDL语言写的.PARAMETERS(WIDTH = 4,DEP

请问如下程序是Verilog 还是VHDL语言写的.PARAMETERS(WIDTH = 4,DEPTH = 0);SUBDESIGN altshift(data[(WIDTH - 1)..0] :INPUT;clock :INPUT = GND;aclr :INPUT = GND;clken :INPUT = VCC;result[(WIDTH - 1) ..0] :OUTPUT;)VARIAB